
#include "project.h"
#include "RFprotocol.h"

/**
 * void RF_Wait(unsigned int cycles)
 * 
 * Random Wait Cycles to avoid timing issues!
 * Wait for given amount of cycles with decrements of 6
 */
void RF_Wait(unsigned int cycles)
{
  while(cycles>15)                          // 15 cycles consumed by overhead
    cycles = cycles - 6;                    // 6 cycles consumed each iteration
}


/**
 * void RF_SPISetup(void)
 * 
 * Configures the USCI_B0 as SPI for RF module
 */
 
 void RF_SPISetup(void)
{
	
  RF_CSn_PxOUT |= RF_CSn_PIN;
  RF_CSn_PxDIR |= RF_CSn_PIN;         // /CS disable

  UCB0CTL1 |= UCSWRST;                      // **Disable USCI state machine**
  UCB0CTL0 |= UCMST+UCCKPH+UCMSB+UCSYNC;    // 3-pin, 8-bit SPI master
  UCB0CTL1 |= UCSSEL_2;                     // SMCLK
  //UCB0BR0 = 0x02;                           // UCLK/2
  UCB0BR0 = 0x10;                           // UCLK/4
  UCB0BR1 = 0;
  RF_SPI_USCIB0_PxSEL |= RF_SPI_USCIB0_SIMO
                         | RF_SPI_USCIB0_SOMI
                         | RF_SPI_USCIB0_UCLK;
                                            // SPI option select
  RF_SPI_USCIB0_PxDIR |= RF_SPI_USCIB0_SIMO | RF_SPI_USCIB0_UCLK;
                                            // SPI TXD out direction
  UCB0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  
}

/**
 * void RF_Write(char addr, char value)
 * 
 * Writes "value" to a single configuration register at address "addr".
 */
void RF_Write(char addr, char value)
{
  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = addr;                         // Send address
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = value;                        // Send data
  while (RF_BUSY);                // Wait for TX to complete
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable
}


/**
 *   void RF_BurstWrite(char addr, char *buffer, char count)
 * 
 *   Writes values to multiple configuration registers, the first register being
 *   at address "addr".  First data byte is at "buffer", and both addr and
 *   buffer are incremented sequentially (within the CCxxxx and MSP430,
 *   respectively) until "count" writes have been performed.
 */
void RF_BurstWrite(char addr, char *buffer, char count)
{
  unsigned int i;

  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = addr | RF_CC2500_WRITE_BURST; // Send address
  for (i = 0; i < count; i++)
  {
    while (TX_NOT_DONE);               // Wait for TXBUF ready
    UCB0TXBUF = buffer[i];                  // Send data
  }
  while (RF_BUSY);                // Wait for TX to complete
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable
}

/**
 *	char RF_Read(char addr)
 * 
 *  Reads a single configuration register at address "addr" and returns the
 *  value read.
 */
char RF_Read(char addr)
{
  char x;

  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = (addr | RF_CC2500_READ_SINGLE);// Send address
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = 0;                            // Dummy write so we can read data
  while (RF_BUSY);                // Wait for TX to complete
  x = UCB0RXBUF;                            // Read data
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable

  return x;
}

/**
*  void RF_BurstRead(char addr, char *buffer, char count)
*
*  Reads multiple configuration registers, the first register being at address
*  "addr".  Values read are deposited sequentially starting at address
*  "buffer", until "count" registers have been read.
*/
void RF_BurstRead(char addr, char *buffer, char count)
{
  char i;

  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = (addr | RF_CC2500_READ_BURST);// Send address
  while (RF_BUSY);                // Wait for TX to complete
  UCB0TXBUF = 0;                            // Dummy write to read 1st data byte
  // Addr byte is now being TX'ed, with dummy byte to follow immediately after
  IFG2 &= ~UCB0RXIFG;                       // Clear flag
  while (RX_EMPTY);               // Wait for end of 1st data byte TX
  // First data byte now in RXBUF
  for (i = 0; i < (count-1); i++)
  {
    UCB0TXBUF = 0;                          //Initiate next data RX, meanwhile..
    buffer[i] = UCB0RXBUF;                  // Store data from last data RX
    while (RX_EMPTY);              // Wait for RX to finish
  }
  buffer[count-1] = UCB0RXBUF;              // Store last RX byte in buffer
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable
}

/**
* char  RF_ReadStatus(char addr)
*
* Special read function for reading status registers.  Reads status register
* at register "addr" and returns the value read.
* For status/strobe addresses, the BURST bit selects between status registers
* and command strobes.
*/
char RF_ReadStatus(char addr)
{
  char status;

  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = (addr | RF_CC2500_READ_BURST);// Send address
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = 0;                            // Dummy write so we can read data
  while (RF_BUSY);                // Wait for TX to complete
  status = UCB0RXBUF;                       // Read data
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable

  return status;
}

/**
*  void RF_Strobe(char strobe)
*
*  Special write function for writing to command strobe registers.  Writes
*  to the strobe at address "addr".
*/
void RF_Strobe(char strobe)
{
  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = strobe;                       // Send strobe
  // Strobe addr is now being TX'ed
  while (RF_BUSY);                // Wait for TX to complete
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable
}

void RF_PowerupReset(void)
{
  RF_CSn_PxOUT |= RF_CSn_PIN;
  RF_Wait(30);
  RF_CSn_PxOUT &= ~RF_CSn_PIN;
  RF_Wait(30);
  RF_CSn_PxOUT |= RF_CSn_PIN;
  RF_Wait(45);

  RF_CSn_PxOUT &= ~RF_CSn_PIN;        // /CS enable
  while (TX_NOT_DONE);               // Wait for TXBUF ready
  UCB0TXBUF = RF_CC2500_SRES;               // Send strobe
  // Strobe addr is now being TX'ed
  while (RF_BUSY);               		 // Wait for TX to complete
  RF_CSn_PxOUT |= RF_CSn_PIN;         // /CS disable
}

//------------------------------------------------------------------------------
//  void writeRFSettings(void)
//
//  DESCRIPTION:
//  Used to configure the CCxxxx registers.  There are five instances of this
//  function, one for each available carrier frequency.  The instance compiled
//  is chosen according to the system variable RF_RF_FREQ, assigned within
//  the header file "RF_hardware_board.h".
//
//  ARGUMENTS:
//      none
//------------------------------------------------------------------------------


#if RF_FREQ == 315                          // 315 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 315.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (1)  address check
// FIFO autoflush = 0
// Device address = 1
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    RF_Write(RF_CC2500_IOCFG2,   0x0B); // GDO2 output pin config.
    RF_Write(RF_CC2500_IOCFG0,   0x06); // GDO0 output pin config.
    RF_Write(RF_CC2500_PKTLEN,   PKTLEN); // Packet length.
    RF_Write(RF_CC2500_PKTCTRL1, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_PKTCTRL0, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_ADDR,     0x01); // Device address.
    RF_Write(RF_CC2500_CHANNR,   0x00); // Channel number.
    RF_Write(RF_CC2500_FSCTRL1,  0x0B); // Freq synthesizer control.
    RF_Write(RF_CC2500_FSCTRL0,  0x00); // Freq synthesizer control.
    RF_Write(RF_CC2500_FREQ2,    0x0C); // Freq control word, high byte
    RF_Write(RF_CC2500_FREQ1,    0x1D); // Freq control word, mid byte.
    RF_Write(RF_CC2500_FREQ0,    0x89); // Freq control word, low byte.
    RF_Write(RF_CC2500_MDMCFG4,  0x2D); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG3,  0x3B); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG2,  0x73); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG1,  0x22); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG0,  0xF8); // Modem configuration.
    RF_Write(RF_CC2500_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    RF_Write(RF_CC2500_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_FOCCFG,   0x1D); // Freq Offset Compense. Config
    RF_Write(RF_CC2500_BSCFG,    0x1C); //  Bit synchronization config.
    RF_Write(RF_CC2500_AGCCTRL2, 0xC7); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL1, 0x00); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL0, 0xB2); // AGC control.
    RF_Write(RF_CC2500_FREND1,   0xB6); // Front end RX configuration.
    RF_Write(RF_CC2500_FREND0,   0x10); // Front end RX configuration.
    RF_Write(RF_CC2500_FSCAL3,   0xEA); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL2,   0x0A); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL1,   0x00); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL0,   0x11); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSTEST,   0x59); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_TEST2,    0x88); // Various test settings.
    RF_Write(RF_CC2500_TEST1,    0x31); // Various test settings.
    RF_Write(RF_CC2500_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x51};
extern char paTableLen = 1;

#endif


#if RF_FREQ == 433                          // 433 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 433.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    RF_Write(RF_CC2500_IOCFG2,   0x0B); // GDO2 output pin config.
    RF_Write(RF_CC2500_IOCFG0,   0x06); // GDO0 output pin config.
    RF_Write(RF_CC2500_PKTLEN,   PKTLEN); // Packet length.
    RF_Write(RF_CC2500_PKTCTRL1, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_PKTCTRL0, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_ADDR,     0x01); // Device address.
    RF_Write(RF_CC2500_CHANNR,   0x00); // Channel number.
    RF_Write(RF_CC2500_FSCTRL1,  0x0B); // Freq synthesizer control.
    RF_Write(RF_CC2500_FSCTRL0,  0x00); // Freq synthesizer control.
    RF_Write(RF_CC2500_FREQ2,    0x10); // Freq control word, high byte
    RF_Write(RF_CC2500_FREQ1,    0xA7); // Freq control word, mid byte.
    RF_Write(RF_CC2500_FREQ0,    0x62); // Freq control word, low byte.
    RF_Write(RF_CC2500_MDMCFG4,  0x2D); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG3,  0x3B); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG2,  0x73); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG1,  0x22); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG0,  0xF8); // Modem configuration.
    RF_Write(RF_CC2500_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    RF_Write(RF_CC2500_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_FOCCFG,   0x1D); // Freq Offset Compens. Config
    RF_Write(RF_CC2500_BSCFG,    0x1C); //  Bit synchronization config.
    RF_Write(RF_CC2500_AGCCTRL2, 0xC7); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL1, 0x00); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL0, 0xB2); // AGC control.
    RF_Write(RF_CC2500_FREND1,   0xB6); // Front end RX configuration.
    RF_Write(RF_CC2500_FREND0,   0x10); // Front end RX configuration.
    RF_Write(RF_CC2500_FSCAL3,   0xEA); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL2,   0x0A); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL1,   0x00); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL0,   0x11); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSTEST,   0x59); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_TEST2,    0x88); // Various test settings.
    RF_Write(RF_CC2500_TEST1,    0x31); // Various test settings.
    RF_Write(RF_CC2500_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x51};
extern char paTableLen = 1;

#endif


#if RF_FREQ == 868                          // 868 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 868.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    RF_Write(RF_CC2500_IOCFG2,   0x0B); // GDO2 output pin config.
    RF_Write(RF_CC2500_IOCFG0,   0x06); // GDO0 output pin config.
    RF_Write(RF_CC2500_PKTLEN,   PKTLEN); // Packet length.
    RF_Write(RF_CC2500_PKTCTRL1, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_PKTCTRL0, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_ADDR,     0x01); // Device address.
    RF_Write(RF_CC2500_CHANNR,   0x00); // Channel number.
    RF_Write(RF_CC2500_FSCTRL1,  0x0B); // Freq synthesizer control.
    RF_Write(RF_CC2500_FSCTRL0,  0x00); // Freq synthesizer control.
    RF_Write(RF_CC2500_FREQ2,    0x21); // Freq control word, high byte
    RF_Write(RF_CC2500_FREQ1,    0x62); // Freq control word, mid byte.
    RF_Write(RF_CC2500_FREQ0,    0x76); // Freq control word, low byte.
    RF_Write(RF_CC2500_MDMCFG4,  0x2D); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG3,  0x3B); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG2,  0x73); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG1,  0x22); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG0,  0xF8); // Modem configuration.
    RF_Write(RF_CC2500_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    RF_Write(RF_CC2500_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_FOCCFG,   0x1D); // Freq Offset Compens. Config
    RF_Write(RF_CC2500_BSCFG,    0x1C); //  Bit synchronization config.
    RF_Write(RF_CC2500_AGCCTRL2, 0xC7); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL1, 0x00); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL0, 0xB2); // AGC control.
    RF_Write(RF_CC2500_FREND1,   0xB6); // Front end RX configuration.
    RF_Write(RF_CC2500_FREND0,   0x10); // Front end RX configuration.
    RF_Write(RF_CC2500_FSCAL3,   0xEA); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL2,   0x0A); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL1,   0x00); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL0,   0x11); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSTEST,   0x59); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_TEST2,    0x88); // Various test settings.
    RF_Write(RF_CC2500_TEST1,    0x31); // Various test settings.
    RF_Write(RF_CC2500_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x60};
extern char paTableLen = 1;

#endif


#if RF_FREQ == 915                          // 915 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 915.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    RF_Write(RF_CC2500_IOCFG2,   0x0B); // GDO2 output pin config.
    RF_Write(RF_CC2500_IOCFG0,   0x06); // GDO0 output pin config.
    RF_Write(RF_CC2500_PKTLEN,   0xFF); // Packet length.
    RF_Write(RF_CC2500_PKTCTRL1, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_PKTCTRL0, 0x05); // Packet automation control.
    RF_Write(RF_CC2500_ADDR,     0x01); // Device address.
    RF_Write(RF_CC2500_CHANNR,   0x00); // Channel number.
    RF_Write(RF_CC2500_FSCTRL1,  0x0B); // Freq synthesizer control.
    RF_Write(RF_CC2500_FSCTRL0,  0x00); // Freq synthesizer control.
    RF_Write(RF_CC2500_FREQ2,    0x23); // Freq control word, high byte
    RF_Write(RF_CC2500_FREQ1,    0x31); // Freq control word, mid byte.
    RF_Write(RF_CC2500_FREQ0,    0x3B); // Freq control word, low byte.
    RF_Write(RF_CC2500_MDMCFG4,  0x2D); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG3,  0x3B); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG2,  0x73); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG1,  0x22); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG0,  0xF8); // Modem configuration.
    RF_Write(RF_CC2500_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    RF_Write(RF_CC2500_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_FOCCFG,   0x1D); // Freq Offset Compens. Config
    RF_Write(RF_CC2500_BSCFG,    0x1C); //  Bit synchronization config.
    RF_Write(RF_CC2500_AGCCTRL2, 0xC7); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL1, 0x00); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL0, 0xB2); // AGC control.
    RF_Write(RF_CC2500_FREND1,   0xB6); // Front end RX configuration.
    RF_Write(RF_CC2500_FREND0,   0x10); // Front end RX configuration.
    RF_Write(RF_CC2500_FSCAL3,   0xEA); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL2,   0x0A); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL1,   0x00); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL0,   0x11); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSTEST,   0x59); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_TEST2,    0x88); // Various test settings.
    RF_Write(RF_CC2500_TEST1,    0x31); // Various test settings.
    RF_Write(RF_CC2500_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x50};
extern char paTableLen = 1;

#endif



#if RF_FREQ == 2400                          // 2.4GHz
// Product = CC2500
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    RF_Write(RF_CC2500_IOCFG2,   0x0B);  // GDO2 output pin config.
    RF_Write(RF_CC2500_IOCFG0,   0x06);  // GDO0 output pin config.
    RF_Write(RF_CC2500_PKTLEN,   PKTLEN);  // Packet length.
    RF_Write(RF_CC2500_PKTCTRL1, 0x05);  // Packet automation control.
    RF_Write(RF_CC2500_PKTCTRL0, 0x05);  // Packet automation control.
    RF_Write(RF_CC2500_ADDR,     0x01);  // Device address.
    RF_Write(RF_CC2500_CHANNR,   0x00); // Channel number.
    RF_Write(RF_CC2500_FSCTRL1,  0x07); // Freq synthesizer control.
    RF_Write(RF_CC2500_FSCTRL0,  0x00); // Freq synthesizer control.
    RF_Write(RF_CC2500_FREQ2,    0x5D); // Freq control word, high byte
    RF_Write(RF_CC2500_FREQ1,    0x93); // Freq control word, mid byte.
    RF_Write(RF_CC2500_FREQ0,    0xB1); // Freq control word, low byte.
    RF_Write(RF_CC2500_MDMCFG4,  0x2D); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG3,  0x3B); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG2,  0x73); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG1,  0x22); // Modem configuration.
    RF_Write(RF_CC2500_MDMCFG0,  0xF8); // Modem configuration.
    RF_Write(RF_CC2500_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    RF_Write(RF_CC2500_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    RF_Write(RF_CC2500_FOCCFG,   0x1D); // Freq Offset Compens. Config
    RF_Write(RF_CC2500_BSCFG,    0x1C); //  Bit synchronization config.
    RF_Write(RF_CC2500_AGCCTRL2, 0xC7); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL1, 0x00); // AGC control.
    RF_Write(RF_CC2500_AGCCTRL0, 0xB2); // AGC control.
    RF_Write(RF_CC2500_FREND1,   0xB6); // Front end RX configuration.
    RF_Write(RF_CC2500_FREND0,   0x10); // Front end RX configuration.
    RF_Write(RF_CC2500_FSCAL3,   0xEA); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL2,   0x0A); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL1,   0x00); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSCAL0,   0x11); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_FSTEST,   0x59); // Frequency synthesizer cal.
    RF_Write(RF_CC2500_TEST2,    0x88); // Various test settings.
    RF_Write(RF_CC2500_TEST1,    0x31); // Various test settings.
    RF_Write(RF_CC2500_TEST0,    0x0B);  // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0xFB};
extern char paTableLen = 1;

#endif


//-----------------------------------------------------------------------------
//  void RFSendPacket(char *txBuffer, char size)
//
//  DESCRIPTION:
//  This function transmits a packet with length up to 63 bytes.  To use this
//  function, GD00 must be configured to be asserted when sync word is sent and
//  de-asserted at the end of the packet, which is accomplished by setting the
//  IOCFG0 register to 0x06, per the CCxxxx datasheet.  GDO0 goes high at
//  packet start and returns low when complete.  The function polls GDO0 to
//  ensure packet completion before returning.
//
//  ARGUMENTS:
//      char *txBuffer
//          Pointer to a buffer containing the data to be transmitted
//
//      char size
//          The size of the txBuffer
//-----------------------------------------------------------------------------
void RFSendPacket(char *txBuffer, char size)
{
  // the following code is "borrowed" from MRFI
  RF_GDO0_PxIE &= ~RF_GDO0_PIN;       // disable receive interrupts
  RF_Strobe(RF_CC2500_SFRX);          // flush the receive FIFO of any residual data
  RF_Strobe(RF_CC2500_SIDLE);			// set IDLE
  // done MRFI code. Hopefully it works well
  	
  RF_BurstWrite(RF_CC2500_TXFIFO, txBuffer, size); // Write TX data
  RF_Strobe(RF_CC2500_STX);           // Change state to TX, initiating
                                            // data transfer

  while (!(RF_GDO0_PxIN&RF_GDO0_PIN));
                                            // Wait GDO0 to go hi -> sync TX'ed
  while (RF_GDO0_PxIN&RF_GDO0_PIN);
  
  RF_Strobe(RF_CC2500_SFTX);          // flush the FIFO for a clean state 
                                            // taken from MRFI;

                                            // Wait GDO0 to clear -> end of pkt
  RF_GDO0_PxIFG &= ~RF_GDO0_PIN;      // After pkt TX, this flag is set.
                                            // Has to be cleared before existing

  RF_GDO0_PxIE |= RF_GDO0_PIN;        // re-enable receive interrupts

}


// some MRFI definition
#define MRFI_RX_METRICS_SIZE        2
#define MRFI_LENGTH_FIELD_SIZE      1

//-----------------------------------------------------------------------------
//  char RFReceivePacket(char *rxBuffer, char *length)
//
//  DESCRIPTION:
//  Receives a packet of variable length (first byte in the packet must be the
//  length byte).  The packet length should not exceed the RXFIFO size.  To use
//  this function, APPEND_STATUS in the PKTCTRL1 register must be enabled.  It
//  is assumed that the function is called after it is known that a packet has
//  been received; for example, in response to GDO0 going low when it is
//  configured to output packet reception status.
//
//  The RXBYTES register is first read to ensure there are bytes in the FIFO.
//  This is done because the GDO signal will go high even if the FIFO is flushed
//  due to address filtering, CRC filtering, or packet length filtering.
//
//  ARGUMENTS:
//      char *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      char *length
//          Pointer to a variable containing the size of the buffer where the
//          incoming data should be stored. After this function returns, that
//          variable holds the packet length.
//
//  RETURN VALUE:
//      char
//          0x80:  CRC OK
//          0x00:  CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length)
{
  char status[2];
  char pktLen;

  char rxBytesVerify;
  char rxBytes;

  //mrfi code
  rxBytesVerify = RF_Read( RF_CC2500_RXBYTES );
  do
  {
    rxBytes = rxBytesVerify;
    rxBytesVerify = RF_Read( RF_CC2500_RXBYTES );
  }
  while (rxBytes != rxBytesVerify);
  
  if (rxBytes ==0) return 0;
  //end of mrfi code
  
  //if ((RF_ReadStatus(RF_CC2500_RXBYTES) & RF_CC2500_NUM_RXBYTES))
  {
    pktLen = RF_Read(RF_CC2500_RXFIFO); // Read length byte

    if (pktLen > *length)                  // If pktLen size <= rxBuffer
    {
      *length = pktLen;                     // Return the large size

      RF_Strobe(RF_CC2500_SIDLE);	    // set IDLE - MRFI code
      RF_Strobe(RF_CC2500_SFRX);      // Flush RXFIFO
      RF_Strobe(RF_CC2500_SRX);       // RX state - from MRFI
      return 0;                             // Error
    }
    else 
    {
      RF_BurstRead(RF_CC2500_RXFIFO, rxBuffer, pktLen); // Pull data
      *length = pktLen;                     // Return the actual size
      RF_BurstRead(RF_CC2500_RXFIFO, status, 2);
                                            // Read appended status bytes
      return (char)(status[RF_CC2500_LQI_RX]&RF_CC2500_CRC_OK);
    }                                       // Return CRC_OK bit
  }
}

void RF_InterruptEnable(void){
	
	RF_GDO0_PxIES |=  RF_GDO0_PIN;		/*	Falling Edge Interrupt */
	RF_GDO0_PxIN |=  RF_GDO0_PIN;
	RF_GDO0_PxSEL &= ~RF_GDO0_PIN;
	RF_GDO0_PxIFG &= ~ RF_GDO0_PIN;     /*	Clear Flag */
	RF_GDO0_PxIE |=  RF_GDO0_PIN;       /*	Enable Int */
	RF_Strobe(RF_CC2500_SRX);        	/*	Set Recieve Mode */
	
}

